This application relates to integrated circuit (IC) design automation and, more specifically, to gate input protection design.
A conventional approach to designing an IC consists of assembling the IC using standard of-the-shelf IC elements known as cells. Cells are also referred to as logic gates or gates. Automated IC design makes use of a library, table or database of cells (hereafter collectively referred to as the xe2x80x9ccell libraryxe2x80x9d). The structure of IC elements, including MOS devices, is determined by the contents of cells suitably selected from the cell library. Devices such as NMOS (n-type MOS), PMOS (P-type MOS), MOSFET (MOS field effect transistor), CMOS (complimentary MOS), etc., are collectively referred to herein as the MOS devices. Moreover, ICs that include MOS devices are known as MOS ICs or, simply, ICs (hereafter, ICs).
To illustrate the structure of MOS devices in ICs, FIGS. 1a and 1b, show a somewhat simplified cross section of an IC 1 with a MOS transistor 10 or 20. The MOS transistor 10 in FIG. 1a is a p-channel transistor. The MOS transistor 20 in FIG. 1b is an n-channel transistor. The MOS transistors 10 and 20 are shown as being produced in lightly doped p-type and n-type silicon substrates 12 and 22, respectively. A typical MOS transistor includes source, drain and channel regions, as well as a gate separated from these regions by a thin layer of (dielectric) insulation.
Hence, as is further shown, for each of the MOS transistors 10 and 20, two heavily doped n-type and p-type regions, respectively, are created in the substrate 12 and 22. The heavily doped regions in the MOS transistor 10 are indicated as n+ source 14a and n+ drain 14b. The heavily doped regions in the MOS transistor 20 are indicated as p+ source 24a and p+ drain 24b. 
In MOS transistor 10, the channel 2 in the n-type substrate 12 between the source 14a and drain 14b is a region of p-type material. In MOS transistor 20, the channel 4 in the p-type substrate 22 between the source 24a and drain 24b is a region of n-type material. Through the channel 2 (and 4), a current of the majority of charge carriers flows from the source 14a (and 24a) to the drain 14b (and 24b).
In order to insulate the gate 16, as previously described, the gate 16 (and 26) is overlaid on a thin layer of insulating material 18 (and 28) that rests over the surface of the structure. The insulating material has dielectric properties. The thin layer of insulation is grown, for example, as a layer of silicon dioxide (SiO2), and the gate area is formed from a metal such as polysilicon. The gate covers substantially the entire channel region.
Furthermore, holes or vias (not shown) are cut or etched into the thin layer of insulation to make room for metal contacts. The metal contacts, designated as S, G and D, provide electrical connections to the source 14a and 24a, drain 14b and 24b and gate 16 and 26, respectively.
As a result of their physical structure, MOS transistors exhibit certain inherent characteristics including a gate capacitance. More specifically, the metal area of the gate 16 and 26, in conjunction with the dielectric thin layer of insulation 18 and 28 and the channel, form a parallel plate capacitor. This capacitor is known as the gate capacitor. The insulation layer under the gate area 16 (and 26) is referred to as the gate oxide layer or, simply, gate oxide.
To illustrate the structure of a plurality of MOS devices in an IC, FIGS. 1c and 1d show a somewhat simplified cross section of ICs 100 and 200 with a plurality of MOS transistors 110, 120, 210 and 220, respectively. Each of the MOS transistors 110, 120, 210 and 220 is structured in a manner as explained above. In FIG. 1c, the MOS transistors 110 and 120 are constructed in a p-type substrate, where the p+ regions of the source 114a and drain 114b in MOS transistor 110 are diffused into an n-type well 118. Conversely, in FIG. 1d, the MOS transistors 210 and 220 are constructed in an n-type substrate, where the n+ regions of the source 224a and drain 224b in MOS transistor 210 are diffused into a p-type well 218.
Regions of insulation shown as the silicon dioxide (SiO2) regions 128 (and 228) separate between adjacent MOS transistors. For example, insulation region 128b (and 228b) separates between adjacent MOS transistors 110 and 120 (and 210 and 220) in IC 100 (and 200). Moreover, for each MOS transistor, the metal area of the respective gates 116 and 126 (and 216 and 226), in conjunction with the dielectric thin layer of insulation 130 (and 230) and the channel (not shown), forms a parallel plate capacitor. For each MOS transistor, this capacitor is its gate capacitor, and the insulation layer 130 (and 230) under the gate area is its gate oxide layer or, simply, the gate oxide.
After assembling the thousands of unconnected cells for creating the IC, the interconnection of the cells can be achieved by a metallization process. Metallization includes the creation of a metal layer for interconnecting between the cells. A metal layer is made out of a conductive material (e.g., metal) according to a pattern specified to implement the particular IC function. In automated IC design, the metal layer pattern is created by routing that implements the specified IC function. The metal layer is processed according to the routed pattern. For example, in the production of CMOS devices, plasma etching techniques are used to produce the pattern on the metal layer.
Metal layers are individually created and then connections are made between them as needed. This allows interconnections defined by pattern of the various metal layers to carry signals to and from cells in similar or different levels. FIGS. 2a and 2b show a somewhat simplified diagram of an IC 300 with a plurality of partially connected MOS transistors 302 and 304.
Interconnects in one metal layer (M2) 342 and 344 may be connected to several gate inputs 316 and 326 of MOS transistors 302 and 304 before connections between this (M2) and other metal layers (M3) 340 can be completed. Until the connections are completed, such gates remain open circuited and the interconnects that are attached to them behave as antennas. The antenna-behaving interconnects receive static charge from the surrounding environment when, for example, a next higher metal layer (M3) 340 is plasma-etched. It may be recalled that each gate is associated with a gate capacitor (not shown). For that reason, the static charge 350 is induced by the antenna-behaving interconnects at the respective gate inputs 316 and 326 as a collection of charges at their gate capacitors.
Charges 350 that accumulate in a gate capacitor can cause a gate-to-source voltage (VGS) 360 and 370 to exceed a breakdown voltage. An accumulation of charges on an open-circuited gate may result in a large enough field to punch through the dielectric gate oxide. Since a gate oxide is extremely thin, it may easily be damaged by the excessive voltage. This effect is magnified as the length of interconnects increases.
As the density of MOS devices in IC increases, the structure of MOS devices gets smaller and, in turn, their respective gate oxide layers become even thinner. Moreover, to achieve higher performance and reduce power consumption, MOS devices, particularly CMOS devices, have been operating under lower supply voltage conditions and with smaller gate sizes. Hence the accumulation of charges due to the antenna behavior of the interconnects becomes more critical.
To prevent the accumulation of static charge in the gate capacitor of MOS devices, gate protection is usually included at the gate input of the MOS devices. The protection mechanism invariably makes use of clamping or antenna diodes (hereafter collectively referred to as antenna diodes). The function of the gate input protection is to limit the gate input voltage and prevent breakdown of the gate.
FIGS. 2c and 2d, illustrate a cross section of an IC 12 (and 22) with an antenna diode 18 connected at the gate input of MOS transistor 10 (and 20). The antenna diode prevents the gate-to-source voltage from exceeding the supply voltage by more than the diode-on voltage (i.e.,
VGSxe2x89xa6VDD+VD,
where VGS is the gate-to-source voltage, VDD is the supply voltage and VD is the diode-on voltage).
If the interconnect length could be controlled, a p-n or n-p junction diode could be added to each input. However, with automatic placement of cells and routing this approach is too difficult to control. Hence, in ICs the protection mechanism can be included in the cells. And, in order to prevent breakdown of MOS devices in an IC, the MOS devices are provided by selecting cells from the library that have the input protection devices.
FIGS. 3a-c illustrate an IC with an antenna diode connected at the gate input of each MOS transistor. In FIGS. 3a and 3b, the partially connected MOS transistors 302 and 304 and MOS transistor 306 which provides the signal (i.e., the signal source) are each configured with an antenna diode 308, 318 and 328 for gate input protection. As a further example, in FIG. 3c, the partially connected CMOS transistors 402 and 404 and CMOS transistor 406 of IC 400 are each provided with a pair of antenna diodes 408, 418 and 428 for gate input protection.
Having the diodes at each of the gate inputs in the IC protects the gates from breakdown but increases the input capacitance of MOS devices at the connection point to the respective interconnects. This reduces the overall IC performance because the signals carried by the interconnects encounter higher load capacitances and, in turn, longer charge time and lower overall speed.
Hence, a need exists for providing high performance ICs. A need further exists for providing ICs that, in addition to the high performance, are more reliable. The present invention addresses these and related problems.
The present invention provides gate input protection with a reduced number of antenna diodes. The number of antenna diodes can be reduced to a suitable minimum in order to achieve a higher speed. Minimizing the number of antenna diodes in an integrated circuit (IC) in accordance with the invention does not
compromise gate input protection measures to prevent breakdown. Reducing the number of antenna diodes improves the overall performance of ICs also in terms of power consumption. Thus, an IC design that implements the present invention achieves higher performance and reliability.
Typically, an interconnect may have portions thereof placed in more than one metal layer. While the metal layers are not yet interconnected, all or parts (segments) of the interconnect are open and not yet connected to a signal source. The signal source can be external to or internal in the IC. An internal signal source can be, for example, an output of a gate. Hence, before a decision about reducing the number of antenna diodes is made a metal layer and metal layers below it are checked to find out if there are any segments of interconnects to gate inputs that are not yet connected to a signal source. Further, a ratio is established for each interconnect to a gate input that is not yet connected to the signal source. The ratio relates to the physical characteristics of the gate and interconnect and is expressed as the relationship between the areas of the gate and interconnect. The ratio is then compared to an upper limit. Finally, based on this comparison and the number of gate inputs attached to the interconnect segments, a decision is made whether to reduce the number of antenna diodes that are either already present or to be later added. Once a decision is made, the number of antenna diodes that are associated with gate inputs is adjusted accordingly by removing or adding less antenna diodes.
In accordance with a purpose of the invention, a computer system can be used in which an embodiment of the invention is implemented. The embodiment can be implemented in the computer system as a separate design automation tool or as part of other design automation tools. The invention can be embodied in the computer system in the form of computer program code stored in a computer readable medium.
Thus, in accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method for reducing the number of antenna diodes for gate input protection in the IC. In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a computer readable medium embodying computer program code configured to cause a computer system to perform steps for reducing the number of antenna diodes.
In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention also related to a system for reducing the number of antenna diodes. The system includes a processor and a storage medium embodying computer program code executed by the processor. The storage medium includes a circuit design engine, a physical data generator, and a diodes number minimizing engine capable of performing steps for minimizing the number of antenna diodes, as detailed below.
In further accordance with the purpose of the invention, as embodied and described herein, the invention additionally relates to an IC. The IC includes gate inputs. Interconnects routed in one or more metal layers of the IC are attached to at least one of the gate inputs. Gate inputs protection in the IC is designed with a reduced number of antenna diodes provided by a diodes number reduction engine. The diodes number reduction engine is capable of performing steps as hereafter described. The gate inputs are provided by a circuit design engine, physical data generator and placement tool. The interconnects are routed by a placement and routing tool.
The steps include selecting a segment of an interconnect routed in a metal layer of an IC and metal layers below the metal layer, and determining whether the selected interconnect segment is attached to any gate input and, if so, further determining whether the selected interconnect is connected to a signal source. The steps further include determining if the selected interconnect segment is at the lowest metal layer for the routed interconnect and, if so, reducing to zero the number of antenna diodes associated with each gate input that is attached to the selected interconnect segment if, in addition, the selected interconnect is already connected to a signal source. The steps additionally include determining whether to adjust the number of antenna diodes associated with gate inputs that are attached to the selected interconnect segment if the selected interconnect segment is not yet connected to the signal source.
The determination of whether to adjust the number of antenna diodes includes determining an interconnect area, determining a gate area, determining a ratio between the interconnect area and the gate area, determining, based on criteria, whether to adjust the number of antenna diodes and, finally, reducing the number of antenna diodes if it is so determined.
The steps are suitably performed with any gate input configuration and, particularly, when, of the gate inputs that are attached to the selected interconnect segment, at least one gate input is initially configured with an associated antenna diode, wherein the number of antenna diodes is reduced by removing antenna diodes. Likewise, the steps are suitably performed when the gate inputs that are attached to the selected interconnect segment are initially configured without an associated antenna diode, wherein an antenna diode can be added to each corresponding gate input configuration, and wherein the number of antenna diodes is reduced by reducing the number of added antenna diodes.
The foregoing steps are followed by additional steps that include, one at a time until all interconnect segments of the routed interconnect have been selected, selecting an additional segment and repeating the forgoing steps for each segment. Moreover, the additional steps include selecting, one at a time, additional routed interconnects for the particular signal route, and repeating the foregoing steps for each of the selected routed interconnects. Finally, if more signal routes remain to be examined, one at a time, each of these signal routes is treated as in the foregoing steps. In other words, each signal route is examined individually, the interconnects of each signal route are examined individually and, in turn, the segments of each interconnect are examined individually.
For each next selected segment, the additional steps includes reducing to zero the number of antenna diodes associated with each gate input that is attached to the next selected segment if the next selected segment is connected to any signal source and is at the lowest metal layer of the routed interconnect. The additional steps further include determining whether to adjust the number of antenna diodes associated with gate inputs that are attached to the next selected segment if the next selected segment is not yet connected to any signal source.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.